Technical Field
The present disclosure generally relates to frequency division, and more particularly to a multi-modulus frequency divider and an electronic apparatus including the same.
Description of the Related Art
A multi-modulus divider (MMD) is a frequency division module that is widely used in conventional phase-locked loop (PLL) technology. A MMD circuit includes a plurality of cascaded frequency divider cells (for example: frequency divider cells that divide by 2 or 3, herein abbreviated as DIV2/3). The frequency divider cells are configured to generate a corresponding output frequency based on an input frequency and a division factor/ratio (divisor).
A basic MMD structure includes a continuous frequency division range of 2N˜2N+1−1. In some mixed logic circuits, the frequency division range may be extended to 2N−M˜2N+1−1.
Currently, a MMD including a plurality of DIV2/3 cells is primarily based on the following two methods. The first method is based on single-end clock signal cascading at complementary metal-oxide-semiconductor (CMOS) level, and is primarily employed in a multi-modulus divider having relatively lower frequency (generally less than 2 GHz). The second method is based on differential signal cascading of current mode logic (CML), and is primarily employed in high-speed radio frequency (RF) circuit, but requires high power consumption.
With the continuous scaling in chip process technology node, increase in operating frequency, and increasing demand for low power consumption, there arises a need for a MMD that can maintain low power consumption while operating in the radio frequency (RF) band. However, the conventional MMD including the plurality of DIV2/3 cells is unable to meet the aforementioned need.